Collars for under-bump metal structures and associated systems and methods

ABSTRACT

The present technology is directed to manufacturing collars for under-bump metal (UBM) structures for die-to-die and/or package-to-package interconnects and associated systems. A semiconductor die includes a semiconductor material having solid-state components and an interconnect extending at least partially through the semiconductor material. An under-bump metal (UBM) structure is formed over the semiconductor material and is electrically coupled to corresponding interconnects. A collar surrounds at least a portion of the side surface of the UBM structure, and a solder material is disposed over the top surface of the UBM structure.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation of U.S. application Ser. No. 15/684,054, filed Aug. 23, 2017, which is a divisional of U.S. application Ser. No. 14/853,807, filed Sep. 14, 2015, now U.S. Pat. No. 9,780,052, which are incorporated herein by reference in their entirety.

TECHNICAL FIELD

The present technology is directed generally to semiconductor devices, and in several embodiments more particularly to under-bump metal (UBM) structures for die-to-die and/or package-to-package interconnects.

BACKGROUND

Microelectronic devices, such as memory devices, microprocessors, and light emitting diodes, typically include one or more semiconductor dies mounted to a substrate and encased in a plastic protective covering. Semiconductor dies include functional features, such as memory cells, processor circuits, and interconnecting circuitry. Semiconductor dies also typically include bond pads electrically coupled to the functional features. The bond pads are electrically connected to pins or other types of terminals that extend outside the protective covering for connecting the semiconductor die to busses, circuits, or other assemblies.

Semiconductor die manufacturers are under increasing pressure to reduce the volume occupied by the die and yet increase the capacity and/or speed of the resulting encapsulated assemblies. To meet these demands, semiconductor die manufacturers often stack multiple dies on top of each other to increase the capacity or performance of the device within the limited volume on the circuit board or other element to which the dies are mounted. In many applications, the dies are stacked on each other before being encapsulated to form a three-dimensional package.

The stacked semiconductor dies are typically electrically connected by solder bumps or other electrical connectors that are attached to under-bump metal (UBM) structures. The UBM structures are typically formed by depositing a copper seed structure onto a wafer, forming a mask on the copper seed structure having openings aligned with bond pads on the die, plating copper onto the seed structure, and then plating one or more other materials over the copper to form UBM structures. The top-most material of the UBM structure is typically selected to promote wetting for subsequently forming interconnects on the top-most material. After forming the UBM structures, microbumps of solder material are formed over the top-most material of the UBM structures to serve as interconnects. After forming the UBM structures and microbumps, the mask is removed and the exposed portions of the seed structure are removed using a suitable wet etch to form isolated UBM structures and microbumps. The present technology is directed to improved UBM structures and methods of manufacturing UBM structures.

BRIEF DESCRIPTION OF THE DRAWINGS

Many aspects of the present technology can be better understood with reference to the following drawings. The components in the drawings are not necessarily to scale, but instead emphasis is placed on clearly illustrating the principles of the present technology.

FIG. 1 is a cross-sectional view of a substrate assembly schematically showing a plurality of semiconductor dies in accordance with an embodiment of the present technology.

FIGS. 2A-2H are cross-sectional views schematically illustrating a portion of a semiconductor die at various stages of a method in accordance with an embodiment of the present technology.

FIGS. 3A-3G are cross-sectional views schematically illustrating a portion of a semiconductor die at various stages of a method in accordance with another embodiment of the present technology.

FIG. 4 is a flow chart of a method in accordance with an embodiment of the present technology.

FIG. 5 is a flow chart of a method in accordance with an embodiment of the present technology.

FIG. 6 is a block diagram illustrating a system that incorporates a semiconductor device in accordance with an embodiment of the present technology.

DETAILED DESCRIPTION

Specific details of several embodiments of methods for making semiconductor devices are described herein along with related devices and systems. The term “semiconductor device” generally refers to a solid-state device that includes one or more semiconductor materials. Examples of semiconductor devices include logic devices, memory devices, microprocessors, and diodes among others. Furthermore, the term “semiconductor device” can refer to a finished device or to an assembly or other structure at various stages of processing before becoming a finished device. Depending upon the context in which it is used, the term “substrate” can refer to a wafer-level substrate or to a singulated, die-level substrate. A person having ordinary skill in the relevant art will recognize that suitable steps of the methods described herein can be performed at the wafer level or at the die level. Furthermore, unless the context indicates otherwise, structures disclosed herein can be formed using conventional semiconductor-manufacturing techniques. Materials can be deposited, for example, using chemical vapor deposition, physical vapor deposition, atomic layer deposition, spin coating, and/or other suitable techniques. Similarly, materials can be removed, for example, using plasma etching, wet etching, chemical-mechanical planarization, or other suitable techniques.

Many embodiments of the present technology are described below in the context of UBM structures that are electrically coupled to TSVs, such as through-silicon vias that have electrically conductive plugs or connectors which extend completely through the substrate and/or packaging material when completed. A person having ordinary skill in the relevant art will also understand that the present technology may include embodiments for forming UBM structures on either the first side or the second side of a substrate assembly, and the UBM structures may be used in the context of other electrical connectors associated with a semiconductor assembly. The present technology may accordingly be practiced without several of the details of the embodiments described herein with reference to FIGS. 1-6. For ease of reference, identical reference numbers are used to identify similar or analogous components or features throughout this disclosure, but the use of the same reference number does not imply that the features should be construed to be identical. Indeed, in many examples described herein, identically numbered features have a plurality of embodiments that are distinct in structure and/or function from each other. Furthermore, the same shading may be used to indicate materials in cross section that can be compositionally similar, but the use of the same shading does not imply that the materials should be construed to be identical unless specifically noted herein.

UBM structures and microbumps are attached to an adjacent die using reflow processes. During reflow of a microbump disposed on top of a UBM structure, some material of the microbump (e.g., tin) may react with material of the UBM structure (e.g., copper), which can deleteriously affect the interconnection between the UBM structure and the adjacent die. For example, some of the material from the microbump can out-flow due to sidewall wetting along the UBM structure. This can lead to formation of an intermetallic compound on the microbump sidewall. Additionally, some of the microbump material (e.g., tin) can diffuse until reaching and reacting with the UBM structure material (e.g., copper), resulting in molar volume shrinkage for the available tin in the microbump, also referred to as solder starvation. These two effects can result in depletion of un-reacted solder material available at the center of the microbump, causing voids in the solder joint and reducing the electromigration reliability.

Several embodiments of the present technology significantly reduce the possibility for solder material of a microbump to react with material of a UBM structure during reflow of the microbump. For example, several embodiments of the present technology form a collar around at least a portion of the first material and/or the second material of the UBM structure that protects the UBM sidewalls from reacting with solder from the microbump. Several embodiments of the present technology accordingly reduce the reaction between the microbumps and UBM sidewalls during microbump reflow as explained in more detail below.

FIG. 1 is a cross-sectional view that schematically illustrates a substrate assembly 100 having a semiconductor material 110 with a first side 112 and a second side 114. The substrate assembly 100 further includes a dielectric material 116 on the second side 114 of the semiconductor material 110. A plurality of semiconductor dies 120 are formed at discrete areas of the substrate assembly 100. Although two semiconductor dies 120 are illustrated in FIG. 1, in practice the semiconductor assembly 100 typically has several hundred or even over 1,000 individual semiconductor dies. The individual semiconductor dies 120 can include integrated circuitry 122 and a plurality of interconnects 124 electrically coupled to the integrated circuitry 122. In the embodiment shown in FIG. 1, the interconnects 124 are TSVs that include a dielectric liner 126 and a conductive plug 128 within the dielectric liner 126. The interconnects 124 can accordingly extend completely through the substrate assembly 100.

The semiconductor dies 120 further include a plurality of UBM structures 130, and individual UBM structures 130 are electrically coupled to corresponding interconnects 124. In several embodiments, the individual UBM structures 130 comprise a first material 132 electrically coupled to one of the interconnects 124 and a second material 134 over the first material 132. An anti-wetting material 136 forms a collar 138 around at least a portion of the first material 132 and the second material 134. The semiconductor dies 120 can also include microbumps 140 over the second material 134 of individual UBM structures 130.

In a particular embodiment, the first material 132 comprises copper, the second material 134 comprises nickel, the microbump 140 comprises a tin-silver solder material, and the collar 138 comprises an oxide, for example tetraethyl orthosilicate (TEOS) or another oxide. This embodiment forms a Cu/Ni UBM structure 130 with a microbump 140 formed thereover and an oxide collar surrounding the exposed sidewall of the Ni and at least a portion of the Cu without covering the top surface of the UBM structure 130 (e.g., the top surface of the second material 134). In other embodiments, the first and second materials 132 and 134 can comprise any electrically conductive material, for example, gold, silicon, tungsten, etc. The shape and dimension of the UBM structure 130 can vary. For example, in some embodiments, the UBM structure 130 is substantially cylindrical, forming a pillar-like structure, but the UBM structure 130 can have other cross-sectional shapes in other embodiments, for example rectangular, regular polygonal, irregular polygonal, elliptical, etc. The UBM structure 130 can have a thickness of between about 1-100 microns and can have a height of between about 1-100 microns.

The microbump 140 can comprise a solder material, for example tin-silver, indium, or another suitable solder material for forming an electrical and mechanical connection between the UBM structure 130 and an adjacent die. The anti-wetting material 136 forming the collar 138 can, in some embodiments, comprise a material that prevents wetting of the microbump 140 on the sidewall of the first and second materials 132 and 134 (e.g., the anti-wetting material 136 provides a non-wettable surface for the material of the microbump 140). The anti-wetting material 136 can have a diffusability for the solder material of the microbump 140 that is extremely low or negligible. For example, in some embodiments, the anti-wetting material 136 comprises an oxide, a nitride, or polyimide. In some embodiments, the anti-wetting material 136 has a thickness of between about 1000-5000 Å, or in some embodiments between about 2000-2500 Å. In several embodiments, the anti-wetting material 136 completely surrounds at least a portion of the circumference of the first and/or second materials 132 and 134, but in other embodiments the anti-wetting material 136 covers less than the full circumference. The anti-wetting material 136 also extends along at least a portion of the height of the UBM structure 130; for example the anti-wetting material 136 covers at least 80% of the height of the UBM structure 130. The collar 138 comprising the anti-wetting material 136 eliminates or reduces wetting of solder from the microbump 140 along the sidewall of the first and second material 132 and 134 of the UBM structure 130. Further embodiments and aspects of forming UBM structures, collars, and microbumps in accordance with the present technology are described below with reference to FIGS. 2A-3G.

FIGS. 2A-2H are cross-sectional views schematically illustrating a semiconductor die 120 at a portion of the substrate assembly 100 during different stages of a method for forming UBM structures, collars, and microbumps. Referring to FIG. 2A, at this stage of the method the semiconductor die 120 has a seed structure 240 formed on the dielectric material 116 and the portions of the interconnects 124 proximate to the second side 114 of the substrate 110, and a mask 250 on the seed structure 240. The seed structure 240 can have first areas 242 associated with the location of the interconnects 124 and second areas 244 between the first areas 242. The seed structure 240 can be a single material suitable for plating the base or first material of a UBM structure. In several embodiments, the seed structure 240 includes a barrier material and a seed material on the barrier material. The barrier material can be tantalum, tantalum nitride, titanium, titanium-tungsten or another material that prevents diffusion of the UBM materials into the dielectric material 116 and the substrate 100. The seed material can be copper, a copper alloy, nickel, or other suitable materials for plating the first material 132 (FIG. 1) onto the seed material using electro-plating or electroless-plating techniques known in the art. In practice the seed structure 240 can integrate with the conductive plug 128 of the interconnect 124.

The mask 250 can be a resist material or other suitable mask material having a plurality of openings 252 aligned with the first areas 242 of the seed structure 240. As explained in more detail below, UBM structures are formed in the openings 252 of the mask 250. The openings 252 of the mask 250 have a T-shaped cross-section when viewed from the sides as shown in FIG. 2A, in which an upper portion 254 has a wider opening than a lower portion 256. This T-shaped opening 252 in the mask 250 can be formed using a leaky chrome mask during photolithography or other suitable technique.

FIG. 2B is a cross-sectional view schematically illustrating the semiconductor die 120 after the first material 132 has been formed on the exposed first area 242 (FIG. 2A) of the seed structure 240. In one embodiment, the seed structure 240 includes a copper seed material deposited using a physical vapor deposition process, and the first material 132 comprises copper deposited onto the copper seed material using an electro-plating or electroless-plating process known in the art. The first material 132 can accordingly define a base material of the UBM structure. In one embodiment, the first material 132 has a first diameter (e.g., 30 μm) and a height (30 μm) at this stage of the process, but the diameter and the height of the first material 132 can have any other suitable dimension according to the specific configuration of the particular semiconductor die 120.

FIG. 2C is a cross-sectional view schematically illustrating the semiconductor die 120 after the second material 134 has been deposited into the openings 252 such that the second material 134 is over the first material 132. The second material 134 can comprise nickel or other suitable materials that provide a good wetting surface for forming interconnects on the second material 134. The first material 132 and second material 134 can define a UBM structure 130. At this stage of the process, the semiconductor die 120 has a plurality of UBM structures 130 that are electrically coupled to each other through the seed structure 240. In some embodiments, the second material can be omitted altogether, and the UBM structure can include only the first material.

FIG. 2D is a cross-sectional view schematically illustrating the semiconductor die 120 after a portion of the mask 250 has been removed to define collar openings 258 in accordance with one embodiment of the present technology. The mask 250 can be etched using an anisotropic dry etch and dry clean. The dry etch can remove the mask 250 substantially uniformly across the semiconductor die 120 until it is completely removed in the collar openings 258 adjacent the UBM structures 130. The collar openings 258 can define a thickness of the collars 138 (FIG. 1), for example having a thickness of between about 1000-5000 Å, or between about 2000-2500 Å. The parameters of the dry etch (e.g., chemistry, power, temperature, etc.) can be tailored in order to harden the mask 250 during the etch to prepare the mask 250 for subsequent deposition steps.

FIG. 2E is a cross-sectional view schematically illustrating the semiconductor die 120 after the anti-wetting material 136 has been formed in accordance with one embodiment of the present technology. The anti-wetting material 136 can be a material to which the solder material of the microbump 140 (FIG. 1) does not readily wet (e.g., cover) in liquid phase and/or has low or negligible diffusability for the solder material of the microbump 140 (FIG. 1). The anti-wetting material 136 can be an oxide, a nitride, polyimide, or other suitable material. In one embodiment, the anti-wetting material 136 is tetraethyl orthosilicate (TEOS) formed by low-temperature (e.g., less than 150° C.) plasma-enhanced chemical vapor deposition or other suitable process. The anti-wetting material 136 is formed as a blanket layer over the mask 250 and the openings 252, including covering the UBM structures 130 and filling the collar openings 258 (FIG. 2D).

FIG. 2F is a cross-sectional view schematically illustrating the semiconductor die 120 after portions of the anti-wetting material 136 have been removed in accordance with one embodiment of the technology. A buffered oxide etch or a spacer etch followed by a wet clean can be used to remove portions of the anti-wetting material 136. As shown in FIG. 2F, most of the anti-wetting material 136 has been removed until the only remaining portions of the anti-wetting material 136 are in the collar openings 258 (FIG. 2D) to form the collars 138. In some embodiments, the collars 138 can be substantially coplanar with the second material 134, while in other embodiments the collars 138 can be recessed with respect to the second material 134.

FIG. 2G is a cross-sectional view schematically illustrating the semiconductor die 120 after the microbumps 140 have been formed in accordance with one embodiment of the technology. The microbumps 140 can be formed of solder material, for example tin-silver or indium solder, which is plated into the openings 252 on top of the UBM structure 130 and the collar 138. In some embodiments, the microbumps 140 can have a height of between about 3-50 microns.

FIG. 2H is a cross-sectional view schematically illustrating the semiconductor die 120 after the mask 250 and portions of the seed structure 240 are removed to electrically isolate the UBM structures 130. The mask 250 can be removed using a wet photoresist strip or other suitable technique, and then the second areas 244 of the seed structure 240 can be removed using a wet etch suitable for removing the materials of the seed structure. At this point, the UBM structures are electrically isolated from each other.

FIGS. 3A-3G are cross-sectional views schematically illustrating a semiconductor die 120 at a portion of the substrate assembly 100 during different stages of manufacturing UBM structures, collars, and microbumps in accordance with another embodiment of the present technology. Referring to FIG. 3A, at this stage of the method the semiconductor die 120 has the seed structure 240 on the dielectric material 116 and the portions of the interconnects 124 proximate to the second side 114 of the substrate 110, and the mask 250 is on the seed structure 240. The seed structure 240 has first areas 242 associated with the location of the interconnects 124 and second areas 244 between the first areas 242. The mask 250 can be a resist material or other suitable mask material having a plurality of openings 252 aligned with the first areas 242 of the seed structure 240. As explained in more detail below, UBM structures are formed in the openings 252 of the mask 250.

FIG. 3B is a cross-sectional view schematically illustrating the semiconductor die 120 after the anti-wetting material 136 has been formed in accordance with one embodiment of the present technology. The anti-wetting material 136 can be a material to which the solder material of the microbump 140 (FIG. 1) does not readily wet (e.g., cover) in liquid phase and/or has low or negligible diffusability for the solder material of the microbump 140 (FIG. 1). The anti-wetting material 136 can be an oxide (e.g., tetraethyl orthosilicate (TEOS) or other oxide), a nitride, polyimide, or other suitable material. In one embodiment, the anti-wetting material 136 is tetraethyl orthosilicate (TEOS) formed by low-temperature (e.g., less than 150° C.) plasma-enhanced chemical vapor deposition or other suitable process. The anti-wetting material 136 is formed as a blanket layer over the mask 250 and the openings 252.

FIG. 3C is a cross-sectional view schematically illustrating the semiconductor die 120 after portions of the anti-wetting material 136 have been removed in accordance with one embodiment of the technology. A spacer oxide etch followed by a wet clean can be used to remove portions of the anti-wetting material 136. As shown in FIG. 3C, the overlying portions of the anti-wetting material 136 have been removed until the only remaining portions of the anti-wetting material 136 are along sidewalls of the openings 252.

FIG. 3D is a cross-sectional view schematically illustrating the semiconductor die 120 after the first material 132 has been formed on the exposed first areas 242 (FIG. 3C) of the seed structure 240 and the second material 134 has been formed over the first material 132. In one embodiment, the seed structure 240 includes a copper seed material deposited using a physical vapor deposition process, and the first material 132 comprises copper deposited onto the copper seed material using an electro-plating or electroless-plating process known in the art. The first material 132 and second material 134 can define a UBM structure 130 surrounded by the anti-wetting material 136. At this stage of the process, the semiconductor die 120 has a plurality of UBM structures 130 that are electrically coupled to each other through the seed structure 240. In some embodiments, the second material can be omitted altogether, and the UBM structure can include only the first material.

FIG. 3E is a cross-sectional view schematically illustrating the semiconductor die 120 after further portions of the anti-wetting material 136 have been removed to form the collars 138. Similar to the process described above with respect to FIG. 3B, the additional portions of the anti-wetting material 136 can be removed using a spacer oxide etch followed by a wet clean. As shown in FIG. 3E, the anti-wetting material 136 has been removed until the only remaining anti-wetting material 136 along sidewalls of the openings 252 is substantially coplanar with the second material 134 and thereby forms the collar 138.

FIG. 3F is a cross-sectional view schematically illustrating the semiconductor die 120 after the microbumps 140 have been formed. The microbumps 140 can be formed of solder material, for example tin-silver or indium solder, which is plated into the openings 252 on top of the UBM structure 130 and the collar 138. In some embodiments, the microbumps 140 can have a height of between about 3-50 microns.

FIG. 3G is a cross-sectional view schematically illustrating the semiconductor die 120 after the mask 250 and seed structure 240 are removed to electrically isolate the UBM structures 130. The mask 250 can be removed using a wet photoresist strip or other suitable technique, and then the second areas 244 of the seed structure 240 can be removed using a suitable wet etch to electrically isolate the UBM structures 130 from each other.

FIG. 4 is a flow chart of an embodiment of a method 400 for forming UBM structures on a semiconductor die in accordance with an embodiment of the present technology. In this embodiment, the method 400 includes forming a mask on a seed structure (block 402) and plating a first material onto the exposed areas of the seed structure (block 404). The mask, for example, has openings that expose areas of the seed structure which are electrically coupled to interconnects that extend at least partially through a semiconductor substrate. In several embodiments, the openings of the mask are superimposed over TSVs. The method 400 further includes depositing a second material into the openings over the first material thereby forming a UBM structure (block 406), and etching a collar region around the UBM structure (block 408). The method continues by forming an anti-wetting material over the UBM structure and into the collar region (block 410), followed by etching the anti-wetting material until it is substantially co-planar with the second material in the collar region (block 412). This step forms a collar surrounding the UBM structure. The method 400 continues by forming a microbump over the UBM structure (block 414). The mask can then be removed, followed by removal of the exposed portions of the seed structure between the UBM structures by wet etching.

FIG. 5 is a flow chart of an embodiment of a method 500 for forming UBM structures on a semiconductor die in accordance with an embodiment of the present technology. In this embodiment, the method 500 includes forming a mask on a seed structure (block 502) and forming an anti-wetting material over the mask and the exposed portions of the seed material (block 504). The mask, for example, has openings that expose areas of the seed structure which are electrically coupled to interconnects that extend at least partially through a semiconductor substrate. In several embodiments, the openings of the mask are superimposed over TSVs. The method 500 further includes etching the anti-wetting material until the seed structure is exposed and the remaining anti-wetting material defines a collar in the openings (block 506). For example, the anti-wetting material can be etched using a buffered oxide etch or a spacer etch followed by a wet clean. The method 500 continues by plating a first material over the seed material in the opening (block 508) and forming a second conductive material over the first conductive material in the opening, thereby forming a UBM structure (block 510). The method 500 then removes the anti-wetting material until the collar is substantially coplanar with the second conductive material in the opening (block 512). The method 500 continues by forming a microbump over the UBM structure (block 514). The mask can then be removed, followed by removal of the exposed portions of the seed structure between the UBM structures by wet etching.

Any one of the semiconductor devices having the features described above with reference to FIGS. 1-5 can be incorporated into any of a myriad of larger and/or more complex systems, a representative example of which is system 600 shown schematically in FIG. 6. The system 600 can include a processor 602, a memory 604 (e.g., SRAM, DRAM, flash, and/or other memory devices), input/output devices 606, and/or other subsystems or components 608. The semiconductor device 100 described above with reference to FIGS. 1-5 can be included in any of the elements shown in FIG. 6. The resulting system 600 can be configured to perform any of a wide variety of suitable computing, processing, storage, sensing, imaging, and/or other functions. Accordingly, representative examples of the system 600 include, without limitation, computers and/or other data processors, such as desktop computers, laptop computers, Internet appliances, hand-held devices (e.g., palm-top computers, wearable computers, cellular or mobile phones, personal digital assistants, music players, etc.), tablets, multi-processor systems, processor-based or programmable consumer electronics, network computers, and minicomputers. Additional representative examples of the system 600 include lights, cameras, vehicles, etc. With regard to these and other example, the system 600 can be housed in a single unit or distributed over multiple interconnected units, e.g., through a communication network. The components of the system 600 can accordingly include local and/or remote memory storage devices and any of a wide variety of suitable computer-readable media.

From the foregoing, it will be appreciated that specific embodiments of the invention have been described herein for purposes of illustration, but that various modifications may be made without deviating from the scope of the invention. Accordingly, the invention is not limited except as by the appended claims. 

1. A semiconductor die, comprising: a semiconductor material having solid-state components; an interconnect extending at least partially through the semiconductor material; an under-bump metal (UBM) structure electrically coupled to the interconnect, wherein the UBM structure has a top surface, a bottom surface, and a sidewall extending between the top and bottom surfaces, and wherein the UBM structure comprises a first conductive material and a second conductive material disposed over the first conductive material; a collar surrounding at least a portion of the sidewall of the UBM structure such that the collar contacts at least a portion of the first conductive material, wherein the collar is recessed below the top surface of the UBM structure; and a solder material disposed over the top surface of the UBM structure, wherein the collar comprises an anti-wetting material to which the solder material does not readily wet in liquid phase.
 2. The semiconductor die of claim 1, wherein the collar comprises at least one of: an oxide, a nitride, or polyimide.
 3. The semiconductor die of claim 1, wherein the collar has a thickness of between about 1000 Å and about 5000 Å.
 4. The semiconductor die of claim 1, wherein the UBM structure is a pillar, and wherein the collar only partially covers the sidewall of the pillar.
 5. The semiconductor die of claim 1, wherein the collar does not contact the second conductive material.
 6. The semiconductor die of claim 1, wherein the collar does not extend laterally beyond the solder material.
 7. The semiconductor die of claim 1, wherein a side surface of the collar is substantially coplanar with a side surface of the solder material.
 8. The semiconductor die of claim 1, wherein the UBM structure has a height of between about 1-100 microns, and wherein the UBM structure has a thickness of between about 1-100 microns.
 9. The semiconductor die of claim 1, wherein the first conductive material comprises copper and the second conductive material comprises nickel.
 10. The semiconductor die of claim 1, wherein the UBM structure comprises a pillar including: a lower portion comprising copper and having a first side surface; and an upper portion comprising nickel formed over the lower portion, the upper portion having a second side surface, wherein the first side surface is substantially coplanar with the second side surface.
 11. The semiconductor die of claim 10, wherein the collar is in contact with the first side surface but not in contact with the second side surface.
 12. A semiconductor die, comprising: a semiconductor material having solid-state components; an interconnect extending at least partially through the semiconductor material; an under-bump metal (UBM) structure electrically coupled to the interconnect, wherein the UBM structure has a top surface, a bottom surface, and a sidewall extending between the top and bottom surfaces, and wherein the UBM structure comprises a first conductive material and a second conductive material disposed over the first conductive material; a collar surrounding at least a portion of the sidewall of the UBM structure such that the collar contacts at least a portion of the first conductive material but does not contact the second conductive material; and a solder material disposed over the top surface of the UBM structure.
 13. The semiconductor die of claim 12, wherein the collar comprises an anti-wetting material to which the solder material does not readily wet in liquid phase.
 14. The semiconductor die of claim 12, wherein the collar comprises at least one of: an oxide, a nitride, or polyimide.
 15. The semiconductor die of claim 12, wherein a side surface of the collar is substantially coplanar with a side surface of the solder material.
 16. The semiconductor die of claim 12, wherein the UBM structure comprises a pillar including: a lower portion comprising copper and having a first side surface; and an upper portion comprising nickel formed over the lower portion, the upper portion having a second side surface, wherein the first side surface is substantially coplanar with the second side surface.
 17. The semiconductor die of claim 16, wherein the collar is in contact with the first side surface but not in contact with the second side surface.
 18. A semiconductor die comprising: a semiconductor material; an interconnect extending at least partially through the semiconductor material; a pillar structure electrically coupled to the interconnect, wherein the pillar structure includes a lower portion comprising a first conductive material and having a first side surface and an upper portion comprising a second conductive material formed over the lower portion, the upper portion having a second side surface, a collar surrounding at least a portion of the pillar structure such that the collar contacts at least a portion of the first side surface and is recessed from a top surface of the pillar; and a solder material disposed over the top surface of the pillar structure.
 19. The semiconductor die of claim 18, wherein the collar comprises an anti-wetting material to which the solder material does not readily wet in liquid phase.
 20. The semiconductor die of claim 18, wherein a side surface of the collar is substantially coplanar with a side surface of the solder material. 